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Features
* * * * * * * *
Single 3-V Supply Voltage High Power-added Efficient Power Amplifier (Pout Typically 23 dBm) Ramp-controlled Output Power Low-noise Preamplifier (NF Typically 2.1 dB) Biasing for External PIN Diode T/R Switch Current-saving Standby Mode Few External Components Packages: - PSSO20 - QFN20 with Extended Performance
Bluetooth/ISM 2.4-GHz Front-End IC T7024
1. Description
The T7024 is a monolithic SiGe transmit/receive front-end IC with power amplifier, low-noise amplifier and T/R switch driver. It is especially designed for operation in TDMA systems like Bluetooth(R) and WDCT. Due to the ramp-control feature and a very low quiescent current, an external switch transistor for VS is not required.
Figure 1-1.
Block Diagram
RX_ON PU VS_LNA TX
TX/RX/ standby Control
SWITCH_OUT RX R_SWITCH LNA_IN
LNA
LNA_OUT
RAMP
V1_PA V2_PA
PA_IN
PA
V3_PA_OUT
4533H-BLURF-07/07
2. Pin Configuration
Figure 2-1. Pinning PSSO20
R_SWITCH 1 SWITCH_OUT 2 GND 3 LNA_IN 4 VS_LNA 5 GND 6 V3_PA_OUT 7 V3_PA_OUT 8 V3_PA_OUT 9 GND 10 20 PU
Figure 2-2.
Pinning QFN20
18 LNA_OUT 17 GND 16 PA_IN
10
GND VS_LNA GND LNA_IN GND
9 8 7 6 5 4
19 RX_ON
T7024
15 V1_PA 14 GND 13 V2_PA 12 V2_PA 11 RAMP
V3_PA_OUT V3_PA_OUT V3_PA_OUT GND RAMP
11 12 13 14 15 16 17 18 19 20
T7024
3 2 1
SWITCH_OUT R_SWITCH PU RX_ON LNA_OUT
Table 2-1.
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 Slug
Pin Description
Pins QFN20 4 5 6 7 9 8 11 12 13 10 15 16 17 14 19 20 18 1 2 3 Slug Symbol R_SWITCH SWITCH_OUT GND LNA_IN VS_LNA GND V3_PA_OUT V3_PA_OUT V3_PA_OUT GND RAMP V2_PA V2_PA GND V1_PA PA_IN GND LNA_OUT RX_ON PU GND Function Resistor to GND sets the PIN diode current Switched current output for PIN diode Ground Low-noise amplifier input Supply voltage input for low-noise amplifier Ground Inductor to power supply and matching network for power amplifier output Inductor to power supply and matching network for power amplifier output Inductor to power supply and matching network for power amplifier output Ground Power ramping control input Inductor to power supply for power amplifier Inductor to power supply for power amplifier Ground Supply voltage for power amplifier Power amplifier input Ground Low-noise amplifier output RX active high Power-up active high Ground
Pins PSSO20
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V2_PA V2_PA GND V1_PA PA_IN
T7024
3. Absolute Maximum Ratings
Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Parameters Supply voltage Pins VS_LNA, V1_PA, V2_PA, V3_PA_OUT Junction temperature Storage temperature RF input power LNA RF input power PA Symbol VS Tj Tstg PinLNA PinPA Value 6 150 -40 to +125 5 10 Unit V C C dBm dBm
Electrostatic sensitive device. Observe precautions for handling.
4. Thermal Resistance
Parameters Junction ambient PSSOP20, slug soldered on PCB Junction ambient QFN20, slug soldered on PCB Symbol RthJA RthJA Value 19 27 Unit K/W K/W
5. Handling
Do not operate this part near strong electrostatic fields. This IC meets class 1 ESD test requirement (HBM in accordance to EIA/JESD22-A114-A (October 97) and class A ESD test requirement (MM) in accordance to EIA/JESD22-A115A.
6. Operating Range
All voltages are referred to ground (pins GND and slug). Power supply points are VS_LNA, V1_PA, V2_PA, V3_PA_OUT. The table represents the sum of all supply currents depending on the TX/RX mode. Parameters Supply voltage Pins V1_PA, V2_PA and V3_PA_OUT Supply voltage, pin VS_LNA Supply current TX, PSSO20 QFN20 Supply current RX Standby current, PU = 0 Ambient temperature Symbol VS VS IS IS IS IS_standby Tamb -25 Min. 2.7 2.7 Typ. 3.0 3.0 190 165 8 10 +25 +85 Max. 4.6 5.5 Unit V V mA mA mA A C
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7. Electrical Characteristics
Test conditions (unless otherwise specified): VS = 3.0V, Tamb = 25C Parameters Power Amplifier Supply voltage Supply current Standby current Frequency range Gain-control range Power gain maximum Power gain minimum Ramping voltage maximum Ramping voltage minimum Ramping current maximum Power-added efficiency Saturated output power Input matching(2) Output matching(2) Harmonics at Psat = 23 dBm
(1)
Test Conditions Pins V1_PA, V2_PA, V3_PA_OUT TX, PSSO20 TX, QFN20 RX (PA off), VRAMP 0.1V Standby TX TX TX, pin PA_IN to V3_PA_OUT TX, pin PA_IN to V3_PA_OUT TX, power gain (maximum) Pin RAMP TX, power gain (minimum) Pin RAMP TX, VRAMP = 1.75V, pin RAMP TX, PSSO20 TX, QFN20 TX, input power = 0 dBm referred to pins V3_PA_OUT TX, pin PA_IN TX, pins V3_PA_OUT TX, pins V3_PA_OUT TX, pins V3_PA_OUT Standby, pin SWITCH_OUT RX TX at 100 TX at 1.2 k TX at 33 k TX at
Symbol
Min.
Typ.
Max.
Unit
VS IS_TX IS_TX IS_RX IS_standby f Gp Gp Gp VRAMP max VRAMP min IRAMP max PAE PAE Psat Load VSWR Load VSWR 2 fo 3 fo IS_O_standby IS_O_RX IS_O_100 IS_O_1k2 IS_O_33k IS_O_R VS IS
2.7
3.0 190 165
4.6
V mA mA
10 10 2.4 60 28 -40 1.7 1.75 0.1 0.5 30 35 22 35 40 23 < 1.5:1 < 1.5:1 -30 -30 1 1 1.7 7 17 19 2.7 3.0 8 5.5 9 24 42 30 33 -17 1.83 2.5
A A GHz dB dB dB V V mA % % dBm
dBc dBc A A mA mA mA mA V mA
T/R Switch Driver (Current Programming by External Resistor from R_SWITCH to GND)
Switch-out current output
Low-noise Amplifier Supply voltage Supply current Notes:
(3)
All, pin VS_LNA RX
1. Power amplifier shall be unconditionally stable, maximum duty cycle 100%, true CW operation, maximum load mismatch and duration: load VSWR = 10:1 (all phases) 10s, ZG = 50. 2. With external matching network, load impedance 50. 3. Low-noise amplifier shall be unconditionally stable. 4. With external matching components. 5. LNA gain can be adjusted with RX_ON voltage according to Figure 9-16 on page 11. Please note, that for RX_ON below 1.4V the T/R switch driver switches to TX mode.
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T7024
7. Electrical Characteristics (Continued)
Test conditions (unless otherwise specified): VS = 3.0V, Tamb = 25C Parameters Supply current (LNA and control logic) Standby current Frequency range Power gain
(5)
Test Conditions TX (control logic active) Pin VS_LNA Standby, pin VS_LNA RX RX, pin LNA_IN to LNA_OUT RX, PSSO20 RX, QFN20 RX, referred to pin LNA_OUT RX RX, pin LNA_IN RX, pin LNA_OUT
(5)
Symbol
Min.
Typ.
Max.
Unit
IS IS_standby f Gp NF NF O1dB IIP3 VSWRin VSWRout ViH ViL IiH IiL 2.4 0 40 -9 -16 2.4 15 16 2.5 2.1 -7 -14 1
0.5 10 2.5 19 2.8 2.3 -6 -13 2:1 2:1 VS, LNA 0.5 60 0.2
mA A GHz dB dB dB dBm dBm
Noise figure Gain compression 3 -order input interception point Input matching(4) Output matching(4) Logic Input Levels (RX_ON, PU) High input level Low input level High input current Low input current Notes:
rd
= `1' pins RX_ON and PU = `0' = `1' ViH = 2.4V = `0'
V V A A
1. Power amplifier shall be unconditionally stable, maximum duty cycle 100%, true CW operation, maximum load mismatch and duration: load VSWR = 10:1 (all phases) 10s, ZG = 50. 2. With external matching network, load impedance 50. 3. Low-noise amplifier shall be unconditionally stable. 4. With external matching components. 5. LNA gain can be adjusted with RX_ON voltage according to Figure 9-16 on page 11. Please note, that for RX_ON below 1.4V the T/R switch driver switches to TX mode.
8. Control Logic PA and LNA/Antenna Switch Driver
PU 0 0 0 0 1 1 1 1 Notes: RX_ON 0 0 1 1 0 0 1 1 Ramp(1) 0 1 0 1 0 1 0 1 PA off on off on off on off on LNA off off on on off off on on Antenna Switch Driver off off off off on on off off Operation Mode standby (2) (3) (4) (4) TX RX (5)
1. "0" = VRAMP 0.1V, "1" = VRAMP typically 1.75V, 1.3V < VRAMP < 1.83V controls gain and output power, compare Figure 9-6 on page 7 and Figure 9-10 on page 9 2. Only for special operation, e.g. only PA operation, no LNA/switch driver operation 3. Only for special operation, e.g. no switch driver operation 4. Only for special operation 5. Only for special operation, e.g. separate TX/RX antennas, TX and RX operation at the same time
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9. Typical Operating Characteristics
Figure 9-1. LNA (PSSO20): Gain and Noise Figure versus Frequency
20 8 7
Gain
15
6 5
NF
Gain (dB)
10
4 3
5
2 1
0 2000
2200
2400
2600
2800
0 3000
Frequency (MHz)
Figure 9-2.
LNA (N20): Gain and Noise Figure versus Frequency
25 5
20
Gain
4
Gain (dB)
NF
10
2
5
1
0 2000
2200
2400
2600
2800
0 3000
Frequency (MHz)
Figure 9-3.
LNA: NF and Gain versus Temperature
2.5 2.0
NF
1.5
VS = 3 V
Relative gain, relative NF (dB)
1.0 0.5 0.0 -0.5 -1.0 -1.5 -2.0 -2.5 -40
Gain
-20
0
20
40
60
80
Temperature (C)
6
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4533H-BLURF-07/07
NF (dB)
15
3
NF (dB)
T7024
Figure 9-4. LNA: Typical Switch-out Current versus Rswitch
20
16
IS_O(mA)
12
8
4
0 1 10 100 1000 10000 100000 1000000 10000000
Rswitch()
Figure 9-5.
PA (PSSO20): Output Power and PAE versus Supply
50
I_S_TX
250
Pout (dBm), PAE (%)
40
PAE
220
30
190
20
Pout f = 2.4 GHz Vramp = 1.75 V PinPA = 0 dBm
160
10
130
0 2.7 3.1 3.5 3.9 4.3
100 4.7
Supply Voltage (V)
Figure 9-6.
PA (PSSO20): Output Power and PAE versus Ramp Voltage
50
PAE
250
Pout (dBm), PAE (%)
30
Pout
200
10
150
-10
I_S_TX f = 2.4 GHz VS = 3 V PinPA = 0 dBm
100
-30
50
-50 1.2 1.4 1.6 1.8 2.0
0
Vramp (V)
IS_TX (mA)
IS_TX (mA)
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4533H-BLURF-07/07
Figure 9-7.
PA (PSSO20): Output Power and PAE versus Input Power
40 250
PAE Gain
Pout (dBm), PAE (%), Gp (dB)
30
200
20
I_S_TX
150
10
VS = 3 V f = 2.4 GHz Vramp = 1.75 V PinPA = 0 dBm Pout
100
0
50
-10 -40
0 -30 -20 -10 0 10
Input Power (dBm)
Figure 9-8.
PA (PSSO20): Output Power and PAE versus Frequency
50
I_S_TX
250
Pout (dBm), PAE (%)
40
200
30
PAE
150
20
Pout VS = 3 V Vramp = 1.7 V PinPA = 0 dBm
100
10
50
0 2400
2420
2440
2460
2480
0 2500
Frequency (MHz)
Figure 9-9.
PA (QFN20): Output Power and PAE versus Supply Voltage
50 250
Pout (dBm), PAE (%)
40
PAE I_S_TX
220
30
190
20
f = 2.4 GHz Vramp = 1.8 V PinPA = 0 dBm
Pout
160
10
130
0 2.7 3.1 3.5 3.9 4.3
100 4.7
Supply Voltage (V)
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4533H-BLURF-07/07
IS_TX (mA)
IS_TX (mA)
IS_TX (mA)
T7024
Figure 9-10. PA (QFN20) Output Power and PAE versus Ramp Voltage
50
PAE
250
Pout (dBm), PAE (%)
30
Pout
200
10
150
-10
I_S_TX f = 2.4 GHz VS = 3 V PinPA = 0 dBm
100
-30
50
-50 1.2 1.4 1.6 1.8 2.0
0
Vramp (V)
Figure 9-11. PA (QFN20): Output Power and PAE versus Input Power
Pout (dBm), PAE (%), Gp (dB)
50 300
40
Gain
PAE
250
20
I_S_TX VS = 3 V f = 2.4 GHz Vramp = 1.8 V PinPA = 0 dBm
150
10
100
0
Pout
50
-10 -40
0 -30 -20 -10 0 10
Input Power (dBm)
Figure 9-12. PA (QFN20): Output Power and PAE versus Frequency
50
PAE
250
Pout (dBm), PAE (%)
40
200
20
Pout VS = 3 V Vramp = 1.8 V PinPA = 0 dBm
100
10
50
0 2400
2420
2440
2460
2480
0 2500
Frequency (MHz)
IS_TX (mA)
30
I_S_TX
150
IS_TX (mA)
30
200
IS_TX (mA)
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4533H-BLURF-07/07
Figure 9-13. LNA: Supply Current versus Temperature
8.0
Supply current (mA)
7.8 7.6 7.4 7.2 7.0 6.8 6.6 6.4 6.2 6.0 -40 -20 0 20 40 60 80
Temperature (C)
Figure 9-14. PA (PSSO20): Supply Current versus Iramp and Temperature
200
Supply current (mA)
180 160
-40C
140 120 100
0C 40C
80 60 40
80C
20 0 0.1 1.0 10.0 100.0 1000.0
Iramp (A)
Figure 9-15. PA (PSSO20, QFN20): Pout versus VRAMP and Temperature
30
f = 2.4 GHz VS = 3 V Pin = 0 dBm
20
5
Pout (dBm)
10
0
80
25 -15
-10
-40C
-20 1.0 1.2 1.4 1.6 1.8
Vramp (V)
10
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T7024
Figure 9-16. (PSSO20, QFN20): LNA Gain (dB) versus RX_ON (V)
20.0 15.0 10.0 5.0
VS = 3 V
Gain (dB)
0.0 -5.0 -10.0 -15.0 -20.0 -25.0 1.0 1.5 2.0 2.5 3.0
RX_ON (V)
10. Input/Output Circuits
Figure 10-1. Input Circuit PA_IN/V1_PA
V1_PA
PA_IN
GND
Figure 10-2. Input Circuit RAMP/V1_PA
V1_PA
RAMP
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4533H-BLURF-07/07
Figure 10-3. Input Circuit V2_PA
V2_PA
GND
Figure 10-4. Input/Output Circuit V3_PA_OUT
V3_PA_OUT
GND
Figure 10-5. Input Circuit SWITCH_OUT/R_SWITCH
V1_PA
SWITCH_OUT
R_SWITCH GND
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T7024
Figure 10-6. Input Circuit LNA_IN/VS_LNA
VS_LNA
LNA_IN
GND
Figure 10-7. Input Circuit PU/RX_ON
VS_LNA
LNA_IN / PU
Figure 10-8. Output Circuit LNA_OUT
VS_LNA
LNA_OUT
GND
13
4533H-BLURF-07/07
Figure 10-9. Typical Application T7024 (PSSO20 Package)
LNA OUT
PA IN
5.6nH 3.9nH
V1_PA
3p3
RX ON PU
V2_PA
3.9p
PA ramp
20 19 18 17 16 15 14 13 12 11
T7024
1 2 3 4 5 6 7 8 9 10
harm. termination
1p5 R1 1.8p 15nH
PA OUT
0p8
R1 is selected with DIL-switch Pin-diode replaced by LED on application-board
LNA IN V3_PA VS_LNA Switch Out
Blocking capacitors depending on application
14
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T7024
Figure 10-10. Typical Application T7024 (QFN20 Package)
LNA OUT PA IN V1_PA
V2_PA
2.2p 1p 3p3
RX ON PU
1 2 3 4 5 R1 Var
R1 is selected with DIL-switch
20 19 18 17 16 15 14 T7024 13 12 11 6 7 8 9 10
PA ramp harm. termination
2p2
0p8 1.8p 18nH
LNA IN Pin-diode replaced by LED on application-board Switch Out VS_LNA
V3_PA PA OUT
blocking capacitors depending on application
11. Ordering Information
Extended Type Number T7024-TRSY T7024-TRQY T7024-PGPM T7024-PGQM Demoboard-T7024-PGM Demoboard-T7024-TR Package PSSO20 PSSO20 QFN20 QFN20 QFN20 PSSO20 Remarks Tube, Pb-free Taped and reeled, Pb-free Taped and reeled Pb free, halogen free Taped and reeled Pb free, halogen free Evaluation board QFN Evaluation board PSSO MOQ 830 pcs. 4000 pcs. 1500 pcs. 6000 pcs. 1 1
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12. Package Information
0.4 A B
2.15
Package: PSSO20 Dimensions in mm
2.6
6.75 max. B 6.7 max. 0.15 A
6.450.15 4.40.1 C
1.3
0.05+0.09
0.25 0.12 (20x)
5.40.2
0.65 5.85 20
A 11
technical drawings according to DIN specifications
Drawing-No.: 6.543-5078.01-4 Issue: 1; 05.06.01 1 10
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0.575
0.18 max.
T7024
13. Package Information PB Free
Package: QFN 20 - 5 x 5 Exposed pad 3.1 x 3.1 Dimensions in mm Not indicated tolerances 0.05 0.90.1 0.05-0.05 20 1 15 16
+0
5 3.1 20 1
technical drawings according to DIN specifications
5 0.28 0.6
11 10 6
5
0.65 nom. Drawing-No.: 6.543-5094.01-4 Issue: 1; 19.12.02 2.6
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14. Recommended PCB Land Pattern
Figure 14-1. Recommended PCB Land Pattern
B E D A F C
Table 14-1.
Recommended PCB Land Pattern Signs
Sign A B C D E F Description Distance of vias Size of slug pattern Distance slug to pins Diameter of vias Width of pin pattern Distance of pin pattern Size 1.6 mm 3.1 mm 0.33 mm 1 mm 0.3 mm 0.33 mm
15. Revision History
Please note that the following page numbers referred to in this section refer to the specific revision mentioned, not to this document. Revision No. 4533H-BLURF-07/07 History * Put datasheet in a new template * Page 1: Block diagram changed * Page 13: Figure 10-8 changed
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Product Contact
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4533H-BLURF-07/07

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